1. Field of the Invention
The present invention relates to a lithography simulation method and the like.
2. Description of the Related Art
Recently, the integration density of an LSI is rapidly enhanced and the role of a lithography simulation for pattern verification, pattern correction and the like becomes more important. For example, when a device pattern is given, the exposure condition or mask CD is generally optimized. However, there occurs a problem that the cost becomes excessively high when optimization is attained based on the conventional experimental base. Therefore, it is proposed that the exposure condition or mask CD is optimized by use of a lithography simulation. In this case, the precision and operation speed of the lithography simulation are important.
In order to do the lithography simulation for pattern verification with high precision, it is necessary to set a wide area as an object to be calculated with a certain target point on a pattern set as a center. However, if the wide area is set as the object to be calculated, the calculation time becomes excessively long. Therefore, in the actual lithography simulation, a calculation area is determined by comparing calculation times and precisions (for example, refer to SPIE vol. 3051 pp 567 to 577).
However, the calculation area must be made larger as the integration density of the recent LSI is further enhanced. As a result, there occurs a problem that the calculation time for the lithography simulation is increased.
Thus, in the lithography simulation, the precise pattern verification can be attained when the calculation area is made larger, but the processing time is increased. On the other hand, if the calculation area is made small, the processing time can be reduced, but it becomes difficult to attain the precise pattern verification. That is, in the lithography simulation, the trade-off relation is set between the calculation area and the degree of precision of the pattern verification in the lithography simulation.